The present invention relates to an FSK modulating apparatus applicable to a digital data communication system.
As shown in FIG. 1, a conventional FSK modulating apparatus comprises a voltage controlled oscillator (abbreviated as VCO hereinafter) 31 generating an oscillation signal S31 in a frequency band of 20 MHz, a variable (programmable) frequency divider 32 dividing the frequency of the oscillation signal S31 by 418 or 382 in accordance with a space or mark of input data Di to produce a divided output in a 50 KHz frequency band, a phase comparator 33 comparing phases of the divided output from the variable frequency divider 32 and a reference signal of 50 KHz to produce a control voltage for the VCO 31, a reference signal generator 3 generating the reference signal, a low pass filter 34 disposed between the phase comparator 33 and the VCO 31 for removing an undesired component for the phase locked loop operation, a frequency divider 35 dividing the frequency of the VCO 31 output signal by 200 and a low pass filter 36 removing an undesired component to deliver an output FSK modulated signal. The VCO generates an FSK modulation signal having 19.1 MHz in the mark or 20.9 MHz in the space.
It is a common practice according to the conventional FSK modulating apparatus of FIG. 1 to implement a filter having a first-order CR integration circuit as the low pass filter 34 of the phase locked loop. However, there are problems with this kind of filter in that attenuation of a high frequency component is not sufficient and that when the cut-off frequency of the filter is set higher to enhance the response of the PLL loop, the filter cannot sufficiently remove an undesired signal component. Should the response of the PLL loop be lowered, intersymbol interference would occur. The resultant intersymbol interference becomes an obstruction to achieving a high-speed data communication system. On the other hand, when the low pass filter is implemented with a higher-order filter, harmful oscillation or overshoot due to the filter delay is apt to occur. In addition, such implementation suffers from jitter since the divisor of the variable frequency divider is set every period of the phase comparison frequency.